Microcircuit fabrication in semiconductor devices involves the introduction of impurities into extremely small regions of a substrate, which are subsequently interconnected to create components and very large scale integrated (VLSI) circuits. The patterns that define the small regions are created by lithographic processes.
A lithographic process involves spin-coating a layer of photoresist material onto the wafer substrate. The photoresist is selective exposed to a form of radiation, such as ultraviolet light, electrons or x-rays. An exposure tool and mask are used to affect the desired selective exposure. The patterns in the photoresist are formed when the wafer undergoes a subsequent “development” step. The areas of resist remaining after development protect the substrate regions that they cover during a subsequent etch process for the underlying material. A resist may be positive or negative, meaning that the image is either positive or negative with respect to the mask image.
Locations from which resist has been removed are subjected to an etching process to transfer the pattern onto the substrate surface. A plurality of material layers, which may comprise insulating, conductive, and semiconductive material layers, are deposited over the substrate and patterned and etched in this fashion. Some advanced integrated circuits have twenty or more masking layers, for example.
A common technique used to provide electrical isolation between various element regions of a semiconductor wafer is often referred to as shallow trench isolation (STI), or the formation of isolation trenches (IT). This technique is used frequently in the fabrication of memory cells, for example. Typically, a plurality of steps and material layers are deposited and patterned on a wafer substrate, and then the isolation regions are formed within the patterned material layers.
FIG. 1 illustrates a prior art STI technique used to isolate active areas of a semiconductor device such as a memory array. A semiconductor wafer 10 having a crystalline silicon 12 substrate is covered with a layer of pad nitride 13. A thin layer of pad oxide may reside between the silicon substrate 12 and the pad nitride 13, for example (not shown). In this method of providing shallow trench isolation, a photoresist 26 is deposited over the pad nitride 13, and the photoresist 26 is patterned with the desired pattern of the isolation trenches (IT), shown in phantom. The photoresist 26 is then used to mask the semiconductor wafer 10 while an etch process is used to etch away exposed portions of the pad nitride 13 and underlying substrate 12, for example. The isolation trenches IT formed in the silicon 12 and pad nitride 13 are later filled with an insulator such as an oxide, and the wafer 10 is then polished by a chemical-mechanical polish (CMP) process or other removal process, such as a reactive ion etch (RIE), as an example, down to at least the pad nitride layer 13 surface, leaving the oxide in the trenches IT to provide isolation between devices (not shown).
One problem with the STI technique of FIG. 1 is that as these materials are etched, a portion of photoresist 26 is removed. Because the photoresist 26 is removed as the isolation trenches IT are formed, it may be necessary to deposit a relatively large amount of photoresist 26 over the semiconductor wafer surface, when a relatively deep IT is to be formed, such as is necessitated by a vertical cell design, for example. This can be problematic, because the patterned photoresist 26 may have a high aspect ratio, e.g., the height h may be much greater than the width w. The high aspect ratio of the photoresist may also be driven by the shrinking of design ground rules of the device, as is the trend in the semiconductor industry, to achieve improved performance and higher speed. Because the patterned photoresist 26 is very tall and thin, the patterned photoresist 26 may collapse in certain regions, as shown in phantom in FIG. 1 at 28, resulting in a poor image transfer. Furthermore, a thin resist is needed for small ground rules for acceptable image definition.
Because resist 26 thinning is needed for good image definition and collapse prevention, a hard mask 34 is frequently used between the pad nitride 13 and the photoresist 26, as shown in the prior art drawing of FIG. 2. The hard mask 34 typically comprises either boron-doped silicon glass (BSG), polysilicon, or tetraethoxysilane (TEOS), as examples. An anti-reflective coating (ARC), (not shown), comprising, for example, an organic polymer or a dielectric material, may be deposited over the hard mask 34, and a photoresist 26 typically comprising an organic polymer is deposited over the ARC. ARC is used to reduce reflection during exposure because reflection can deteriorate the quality of the image being patterned.
The photoresist 26 is patterned using lithography techniques and etched to remove exposed portions, and, after an ARC open step, the semiconductor wafer 10 is exposed to an etch process, e.g. an anisotropic etch in a plasma reactor, to transfer the resist 26 pattern to the hard mask 34, as shown in FIG. 2. Reactive ion etching (RIE) is often used to transfer the pattern from the photoresist 26 to the hard mask 34, for example. Portions of the wafer 10 not covered by the hard mask 34 and photoresist 26 are then etched to form isolation trenches IT within the wafer 10 using the photoresist 26 and hard mask 34 to pattern the isolation trenches IT, as shown in phantom in FIG. 2. An insulating material (not shown) is then deposited over the wafer 10, as described for FIG. 1, to provide isolation between the various regions of the wafer 10.
A problem with the process shown and described with reference to prior art FIG. 2 is that while the hard mask (HM) 34 is less susceptible to removal during the formation of the isolation trenches IT, the hard mask 34 thickness needs to be increased for IT depth in a vertical/planar cell. A vertical/planar cell comprises vertical regions 15 comprising vertical devices and planar regions 17 comprising planar or horizontal devices, as shown in FIG. 3. Transistors in the planar regions 17 have a source and drain disposed horizontally across the wafer 10 surface, while vertical regions 15 have transistors with a vertical source and drain, for example.
Referring again to FIG. 2, the patterning of the entire thickness of the hard mask 34 often cannot be completed successfully with the thin resist 26 dictated by collapse and image constraints. One anticipated solution to this problem is to increase photoresist/hard mask 26/34 selectivity by use of high carbon to fluorine (C/F) ratio gases. However, this solution leads to bread-loafing 36, which tends to occur at the top surface of the photoresist 26, as shown in FIG. 2 at 36. This occurs because during the etch process, which typically comprises an RIE process, additional polymer material is deposited on top of the photoresist 26. The bread-loafing 36 forms as a result of the RIE process. The bread-loafing 36 makes the photoresist 26 thicker at top corners, and creates a re-entrant profile or over-etched regions 30 in the regions being etched, resulting in a structure such as the one shown. The bread-loafing 36 leads to poor critical dimension (CD) control, and is undesirable.
Patterning an underlying semiconductor wafer 10 having a variety of different layers of differing materials, such as oxides, nitrides, and various forms of semiconductor material layers proves very challenging, because each of these materials etches at different rates and is more susceptible to etching with various chemistries. As ground rules shrink, patterning semiconductor wafers 10 having complex and varying material layers becomes more and more difficult.
What is needed in the art is an improved method of providing shallow trench isolation that does not have the re-entrant profiles (which are not conducive to void-free filling of insulating materials) that result from prior art processes, and provides smooth slightly sloping sidewalls, in particular for smaller-scale ground rules.